Handel-C Design of a Packet Processing Device for platform-FPGAs
نویسندگان
چکیده
Handel-C is a convenient tool for high-level design for FPGAs. Platform FPGAs, with high-levels of integration are suitable as packet processing devices. An existing ATM packet-switching design has been augmented with a CAM, with a simplified control structure, by the addition of a back-pressure mechanism, and a new shared-memory buffering scheme. The paper gives details of the Handel-C implementation, which demonstrates competitive switching performance for aVirtex FPGA.
منابع مشابه
Parameterised floating-point arithmetic on FPGAs
This paper describes the parameterisation, implementation and evaluation of floating-point adders and multipliers for FPGAs. We have developed a method, based on the Handel-C language, for producing technology-independent pipelined designs that allow compile-time parameterisation of design precision and range, and optional inclusion of features such as overflow protection, gradual underflow and...
متن کاملMulti-spectral Satellite Image Processing on a Platform FPGA Engine
Multi-spectral satellite image sets present a storage and transmission problem. These image sets can also contain line features that typical detection methods do not resolve sharply enough for some purposes. The Karhunen-Loève transform (KLT) presents a solution to both these problems. Firstly, the KLT can be used as a form of lossy data compression, only retaining the higherorder images in the...
متن کاملHow Programmable is Reconfigurable Hardware? : A Design Model for Reconfigurable Architectures
With large-capacity FPGAs, such as the Xilinx Virtex family, complex systems can now be constructed from reconfigurable hardware, and sophisticated designs are more easily implemented through C-language hardware compilers, such as Handel-C [1]. However, improved language support is not enough, as effective system design needs structured methods and high-level design support, which a language by...
متن کاملFormalisation of a Visual Environment for Real Time Image Processing in Hardware (VERTIPH)
We consider the suitability of three types of language for the implementation of image processing algorithms on FPGAs; Hardware Description Languages, Parallel Language Extensions, Serial Language Extensions. We discuss the requirements for a language for this purpose and identify the weaknesses of four specific languages, VHDL, SystemC, Handel-C, SA-C and Match. Finally, we propose VERTIPH, a ...
متن کاملDesign methodology for construction of asynchronous pipelines with Handel-C
CSP channels are proposed as a means of developing high-level, asynchronous pipeline architectures over and above existing synchronous logic. Channel-based design allows hardware systems to be designed and constructed using top-down software engineering methods, which have not previously been available within hardware-software co-design. The intention is to enhance support for future large-scal...
متن کامل